1. Field of the Invention
The present invention relates to a static random access memory having high-resistance elements made of polycrystalline silicon used as load elements within memory cells, and more particularly, to a static random access memory provided with a means for detecting any defective memory cells having leakage current.
2. Description of the Related Art
An E/R (Enhancement type MOS transistor/resistor) type static random-access memory cell (E/R type SRAM cell) is known. As is understood from the equivalent circuit diagram shown in FIG. 1, this memory cell comprises a flip-flop circuit. The flip-flop circuit is comprised of two inverters, each having one high-resistance element, which is used as a load element, and one enhancement type metal oxide semiconductor (MOS) MOS transistor which functions as a drive element. The input and output of the first inverter are connected to the output and input of the second inverter, respectively. More specifically, high-resistance elements R1 and R2 are coupled, at one end, to power-supply voltage V.sub.CC, and at the other end, to the drains of MOS transistors Q1 and Q2, respectively. The sources of MOS transistors Q1 and Q2 are connected to a ground voltage VSS. The gate of transistor Q1 is connected to the drain of transistor Q2, and the gate of transistor Q2 is connected to the drain of transistor Q1. Hence, high-resistance elements R1 and MOS transistor Q1 form an inverter, and high-resistance element R2 and MOS transistor Q2 form another inverter. These inverters have their input and output connected to each other's output and input, respectively, whereby the inverters constitute flip-flop circuit F.
As is illustrated in FIG. 1, MOS transistors Q3 and Q4 are used as transfer gates for controlling data-writing and data-reading. MOS transistor Q3 is connected between memory node N1 of flip-flop circuit F and bit line BL. MOS transistor Q4 is connected between memory node N2 of flip-flop circuit F and bit line BL. The gates of both MOS transistors Q3 and Q4 are connected to word line WL. All transistors Q1 to Q4 are of enhancement type.
The flip-flop circuit F, which is the main component of the memory cell, is a bistable flip-flop. Therefore, two data items which are complementary to each other are stored in memory nodes N1 and N2. Assuming that data items, i.e., "1" and "0", are stored in nodes N1 and N2, respectively, transistor Q1 is off, and transistor Q2 is on. Since high-resistance elements R1 and R2 are linear passive elements, a current flows through high-resistance element R2 coupled to transistor Q2 which is on. The resistance of high-resistance element R2 is far higher than the on-resistance of transistor Q2. Hence, the resistance of element R2 determines the amount of current flowing through transistor Q2. A similar current flows in each of the E/R type SRAM cells forming a static random access memory (SRAM), and the sum of the currents flowing through all E/R type SRAM cells determines the current consumed by the SRAM in its static condition.
Also well known are completely CMOS SRAM cells, each comprising six transistors, two of which are P-channel MOS transistors functioning as load elements. Since the load elements of each completely CMOS RAM cell are active elements, the current which flows in this cell in the static condition is only a leakage current. The current flowing through this cell when the cell is in the static condition is, therefore, small. In contrast, a relatively large current flows through the E/R type SRAM cell when the cell is in the static condition. To reduce this current, high-resistance elements R1 and R2 are replaced with resistors of higher resistances. However, when elements R1 and R2 are replaced by such resistors, the flip-flop F may operate unstably, inevitably destroying the data stored in the E/R type SRAM cell, as will be explained below.
FIG. 2 is a table showing the various resistances which high-resistance elements R1 and R2 of each E/R type SRAM cell must have to maintain the current, which flows through the cell in the static condition, at the typical value of 1 .mu.A, in accordance with the memory capacity of the E/R type SRAM. As may be understood from FIG. 1, memory nodes N1 and N2 exist in the PN junction between a P-type substrate and an N.sup.+ diffusion region which is the common source of transistors Q1 and Q2. The reverse leakage current flowing in this PN junction is about 10.sup.-14 A. This value is equivalent to a resistance of about 100 tera .OMEGA.. In the case of a 256 K-bit memory, the resistance of either high-resistance element, R1 or R2, is 100 times the resistance equivalent to the reverse leakage current flowing in the PN junction. In the case of a 1M-bit memory, the resistance is 25 times the resistance equivalent to the reverse leakage current. The greater the ratio of the resistance of either high-resistance element, the larger the operation margin of each memory cell. As is evident from FIG. 2, this operation margin is inversely proportional to the capacity of the memory.
What has been explained in the preceding paragraph only applies to the case where no abnormal leakage currents flow in the PN junction connected to both memory nodes N1 and N2. In actuality, both a defective leakage current and a contaminating leakage current are generated in the PN junction. When these abnormal leakage currents are far greater than the currents flowing through high-resistance elements R1 and R2, neither memory node can hold the data item "1", and the flip-flop circuit F ceases to function. Hence, the E/R type SRAM cell having this flip-flop circuit F cannot perform its function. Any SRAM chip, including such a defective memory cell, can no longer function at all.
On the hand, when the abnormal leakage currents are nearly equal to the currents flowing through high-resistance elements R1 and R2, the voltage applied on the memory node storing the data item "1" falls to the value determined by the division of resistance achieved by high-resistance elements R1 and R2 and also by the resistance equivalent to the abnormal leakage current. Consequently, flip-flop circuit F becomes very unstable, and the memory cell, as a whole, inevitably operates unstably. Any SRAM which includes such a defective memory cell has neither a sufficient margin for power-supply voltage nor a sufficient margin for temperature changes. Unless the defective memory cell is detected, and appropriate measures are taken for the cell, the data will be destroyed eventually.
However, it is extremely difficult to detect a defective memory in the SRAM. As is known in the art, it takes a long period of time to complete the test for screening an inadequate operation margin or for a defect. In some cases, it is necessary to set the ambient temperature at various values to carry out this test successfully. In the worst case, the insufficient operation margin or the defect may not be detected even if the test has been effected for a considerably long time.
FIG. 3 is an equivalent circuit diagram showing the flip-flop circuit of an E/R type SRAM cell which is identical to the SRAM cell shown in FIG. 1, except that memory nodes N1 and N2 each have a leakage-current path which are shown for illustrative purposes. Resistors Rj and Rj' shown in FIG. 3 are equivalently present on leakage-current paths. More precisely, resistance Rj exists only when a reverse junction coupled to memory node N1, whereas resistance Rj' exists only when a leakage current of an abnormal value flows through the PN junction connected to memory node N2.
The typical temperature characteristics of resistors R1, R2, Rj, and Rj' are illustrated in FIG. 4. As can be understood from FIG. 4, the temperature dependence on the resistivity of high-resistance elements R1 and R2, each formed of a polycrystalline silicon layer, is great. The resistance of resistor Rj is determined by the junction area of memory node N1, and is about 100 tera .OMEGA.. The temperature dependency of resistor Rj is less than that of high-resistance elements R1 and R2. Resistor Rj' has a lower resistance than resistor Rj because of the loss of resistance equivalent to the abnormal leakage current flowing through the PN junction. As is evident from FIG. 4, the line representing the temperature characteristic of resistor Rj' crosses the line representing the temperature characteristic of resistors R1 and R2 at a specific temperature T1 if the resistance of resistor Rj' is about hundreds of times lower than that of resistor Rj. The specific temperature T1 falls within the range in which the memory cell can correctly perform its function. In other words, resistor Rj' has the same resistance as elements R1 and R2 at temperature T1. The resistor Rj' has a resistance lower than that of high-resistance elements R1 and R2 at any temperature below T1, and a resistance higher than that of elements R1 and R2 at any temperature above T1.
The voltage at which memory nodes N1 and N2 hold data when the memory cell is in its static condition will now be calculated. The voltage V1(1) which node N1 requires to hold data "1" can be given: ##EQU1##
The voltage V2(1) which node N2 requires to hold data "1" can be given: ##EQU2##
The voltage Vl(0) which node N1 requires to hold data "0" can be given: ##EQU3##
The voltage V2(0) which node N2 requires to hold data "0" can be given: ##EQU4##
In the above equations (1) to (4), Rn(off) is the resistance equivalent to the channel leakage current which flows when transistors Q1 and Q2 of flip-flop circuit F are off, and Rn(on) is the resistance equivalent to the channel current which flows when transistors Q1 and Q2 are on. Any transistor has Rn(off) as high as 10.sup.14 .OMEGA. or more if operating correctly. Hence, equations (1) to (4) can reduce to: ##EQU5##
It is desirable that the voltages which each memory cell requires to store data "1" and data "0" be V.sub.CC and 0V, respectively. Voltage V2(1), at which memory node N2 holds data "1", is determined by Rj'/R2+Rj', and is lower than V.sub.CC. The lower Rj' is than R2, the more voltage V2(1) will fall. When votage V2(1) falls below the threshold voltage Vthn of each N-channel MOS transistor, Rn(on), one of the terms of equation (3), changes to Rn(off). Consequently, voltage Vl(0), at which memory node N1 holds data "0", will rise to V.sub.CC with time constant of R1.CA (where CA is the capacitance present in memory node N1). That is, data "0" held by node N1 has changed to "1", whereas data "1" held by node N2 has changed to "0". This is the destruction of data. In terms of the temperature characteristics shown in FIG. 4, the data is destroyed at temperature T1 or any lower temperature. This destruction of data is, hence, called "leakage induced cell destruction at low-temperature."
A SRAM memory cell which has undergone low-temperature pause destruction (the destruction of data in a pause mode) cannot be detected unless the SRAM chip is tested not only at room temperature, but also at other various temperatures. It takes an extremely long time to test the SRAM chip at various temperatures, for a memory cell, if any, which has undergone leakage induced cell destruction at low-temperature. Obviously, it is uneconomical to spend much time on testing each SRAM chip. Further, a SRAM cell repeats unstable operation several times until the data stored in it is destroyed completely. This unstable operation of the cell is very hard to detect within a short time of period. It is required to easily and reliably test a wafer having a number of SRAM chips, to determine quickly whether or not each SRAM chip contains any defective memory cells.
Hitherto, in order to detect defective memory cells, if any, contained in a SRAM chip, the operation characteristics of all cells of the SRAM chip are externally examined. This method cannot be completely successful and requires a very long time to test the SRAM chip.